The following apparatuses are conventionally known reconfigurable computing apparatuses. For example, Japanese Laid-Open Patent Publication No. 2005-157653 discloses a data processing apparatus that has processing units and a connection network capable of configuring a first transmission path that serially connects at least a portion of the processing units, and includes a first communication unit that communicates data serially processed by the processing units connected to one another via the first transmission path and a second communication unit that communicates a message to a given processing unit by wormhole routing.
Japanese Laid-Open Patent Publication No. 2004-221997 discloses a reconfigurable circuit that includes a multilevel arrangement of logic circuits, each capable of selectively executing plural computational functions and a connecting unit capable of setting connection relationships between the output of an upstream logic circuit and the input of a downstream logic circuit and further includes an input-dedicated connection line capable of directly inputting data to an intermediate level logic circuit.
Computing elements constituting conventional reconfigurable computing apparatuses have the same bit width, e.g., 16 bits, except when the bit width is temporarily increased to perform rounding processing after multiplication. The same is true for the data processing apparatus disclosed in Japanese Laid-Open Patent Publication No. 2005-157653 and the reconfigurable circuit disclosed in Japanese Laid-Open Patent Publication No. 2004-221997. Thus, conventional configurations have a problem in that when computation is performed at bits less than the bit width of the computing element, the specifications of the mounted computing element are excessive and area efficiency is significantly reduced.
Further, Japanese Laid-Open Patent Publication No. 2005-157653 assumes a configuration of processing units that are computing elements each having the same bit width and thus, does not consider configurations in which one processing unit, i.e., computing element, has a bit width of 4, while another processing unit has a bit width of 8, and still another processing unit has a bit width of 16. Consequently, no technological consideration is given to performing bit compression (rounding), extension (expansion), etc. to convert bit width. In addition, there is no disclosure concerning simultaneous control of connections between processing units, bit width conversion, etc. by a sequencer.